frank-default-large: swap to CIRU v1.1 runtime + jcbtc Qwen3.8-Flash-CIRU-STRIX-IU4

Runtime: ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4 llama.cpp at tag v1.1, built
with the vendor build-linux-amd.sh flag set plus GGML_CUDA_FA +
GGML_CUDA_FA_ALL_QUANTS (the Q4_1_MOE_FORCE_J path is live in the hipified
mmq kernels). Model: jcbtc/Qwen3.8-Flash-CIRU-STRIX-IU4 (Q4_1 IU4 experts,
MTP Q8_0 draft, CIRUPLE1 PLE sidecar) with checksums verified at download.

Vendor production profile verbatim on first deployment: 262144 ctx x 1 slot,
b 2048 / ub 512, t 8 / tb 8, f16 KV, fa on, cont-batching, prompt cache +
8 GiB cache-ram + idle slots, 32 ctx checkpoints (min step 8192), MTP depth
3 with p-split 0.10, PLE pager env knobs (Q41_MOE_FORCE_J=32,
PLE_WORKERS=16, PLE_STRICT_SHA=0, HIPBLASLT=1). Qwen-Sharp chat template
kept deliberately; reasoning stays in DeepSeek format.
This commit is contained in:
Frank
2026-08-29 19:30:04 -07:00
parent d29d2ea29e
commit e22631d892
2 changed files with 143 additions and 111 deletions
+71 -57
View File
@@ -1,44 +1,45 @@
# Tunables for frank-default-large (kingjones777 Qwen3.8-Flash-Next
# ROCmFP4 STRIX, qwen4exp hybrid MoE, Dankclaw, Strix Halo gfx1151).
# Tunables for frank-default-large (jcbtc/Qwen3.8-Flash-CIRU-STRIX-IU4 on
# the ciru-ai Qwen3.8-Flash-CIRU-STRIX-IU4 llama.cpp runtime, tag v1.1,
# Dankclaw, Strix Halo gfx1151 unified memory).
#
# Runtime: ROCmFPX llama.cpp fork with PR #27742 (qwen4exp architecture)
# merged and built at /home/dank/GitPackages/ROCmFPX/build-qwen38.
# Build flags: -DGGML_HIP=ON -DGGML_HIP_ROCMI4_W4A4=ON
# -DCMAKE_HIP_ARCHITECTURES=gfx1151 -DGGML_CUDA_FA_ALL_QUANTS=ON
# -DLLAMA_BUILD_WEBUI=OFF -DCMAKE_EXE_LINKER_FLAGS=-no-pie.
# Replaced the kingjones Qwen3.8-27B Q6_0 AGENT deployment on 2026-09-01.
# Replaced the STRIX_LEAN deployment on 2026-08-27.
# Runtime: full llama.cpp fork at
# /home/dank/GitPackages/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4/build-gfx1151,
# built with the vendor build-linux-amd.sh flag set (HIP on, HIP_NO_VMM on,
# HIP_GRAPHS on, HIP_MMQ_MFMA on, CUDA/VULKAN/SYCL off, gfx1151) plus
# GGML_CUDA_FA + GGML_CUDA_FA_ALL_QUANTS. The IU4 WMMA expert path and the
# CIRUPLE1 PLE pager read the GGML_* env knobs exported by the serve script.
# Replaced the kingjones STRIX_LEAN (ROCmFPX build-qwen38) deployment.
#
# Model: kingjones777/Qwen3.8-Flash-Next-ROCmFP4-STRIX-GGUF.
# 177B params (51.2B PLE n-gram table + 125.8B total MoE/attention).
# Qwen3.8-Flash-Next base: 56B MoE (512 experts, 10 used), 48 layers
# (12 attention + 36 SSM, full_attention_interval=4), 2 KV heads x 256 dim,
# embedding 2560, QSA indexer (4 heads, top_k=2048), hyper-connections
# (count=4, low_rank=320), PLE (layer 1, ngram_size=3, heads_per_ngram=8).
# Q4_0_ROCMFP4_STRIX quant (file_type=105), 113.47 GiB, single GGUF file.
# PLE table: 50.66 GiB Q8_0, streamed from page cache (never in GPU VRAM).
# Text-only (no mmproj). MTP draft head loaded as a separate GGUF sidecar
# (EasiiX/Qwen3.8-Flash-Next-MTP-Strix-Halo-GGUF, Q8_0, 4.1 GB).
# Model: Qwen3.8-Flash-Next base (56B MoE, 512 experts / 10 used, 48 layers
# = 12 attention + 36 SSM, QSA indexer, hyper-connections, PLE at layer 1)
# in the CIRU quality-first mixed quant: 144 routed-expert tensors at Q4_1
# on the native IU4 WMMA path, protected tensors at Q5_K/Q5_1/Q8_0/BF16/F32.
# Main GGUF ~79 GB + MTP Q8_0 draft ~4 GB + exact-FP8 PLE sidecar ~52 GB
# paged from disk (never in VRAM; 4 GiB decoded-page cache via
# --ple-cache-mib). Vendor-validated on the same silicon (gfx1151).
#
# Context: 262144 (256k) x 2 slots. f16 KV cache (~6.4 GiB per slot,
# ~12.8 GiB total). --fit off because the auto-fit code segfaults on this
# model's hyper-connection/indexer config; -ngl 999 places all layers on
# the SVM-backed GPU pool (116 GiB unified).
# The vendor production profile is applied verbatim on this first deployment:
# -ngl all, -sm none, --fit off, ctx 262144 x 1 slot, b 2048 / ub 512,
# t 8 / tb 8, f16 KV, fa on, cont-batching, prompt cache + 8 GiB cache-ram
# + idle-slot cache, 32 ctx checkpoints with min step 8192, MTP depth 3
# with p-split 0.10, GGML_CUDA_Q41_MOE_FORCE_J=32,
# GGML_QWEN4EXP_PLE_WORKERS=16, GGML_QWEN4EXP_PLE_STRICT_SHA=0 (checksums
# were verified with sha256sum -c at download time), ROCBLAS_USE_HIPBLASLT=1.
# The Qwen-Sharp chat template is kept on purpose (chat-template.jinja): the
# service keeps emitting reasoning in DeepSeek format for its clients.
#
# WARNING: do not name any variable TEMP, HOST, or GPU_MAX_HEAP_SIZE. The
# ROCm HIP runtime reads those bare env vars (see the 2026-08-13 TEMP
# incident). llama.cpp reads --host/--port/--temp as CLI flags, never as
# env vars.
# ROCmFPX llama-server (PR #27742 merged, build-qwen38).
LLAMA_BIN=/home/dank/GitPackages/ROCmFPX/build-qwen38/bin/llama-server
# CIRU v1.1 runtime binary (vendor build script, plus FA_ALL_QUANTS).
LLAMA_BIN=/home/dank/GitPackages/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4/build-gfx1151/bin/llama-server
# Model files from
# https://huggingface.co/kingjones777/Qwen3.8-Flash-Next-ROCmFP4-STRIX-GGUF
# STRIX_LEAN (Uncensored) variant, 3-shard Q4_0_ROCMFP4, 98.5 GiB.
MODEL_DIR=/home/dank/models/kingjones-Qwen3.8-Flash-Next-Uncensored-ROCmFP4-STRIX_LEAN
MODEL_FILE=Qwen3.8-Flash-Next-Uncensored-Q4_0-ROCmFP4-STRIX_LEAN-00001-of-00003.gguf
MMPROJ_PATH=/home/dank/models/kingjones-Qwen3.8-Flash-Next-Uncensored-ROCmFP4-STRIX_LEAN/mmproj-Qwen3.8-Flash-Next-Uncensored-BF16.gguf
# Model package from https://huggingface.co/jcbtc/Qwen3.8-Flash-CIRU-STRIX-IU4
# Layout: main GGUF + mtp/ Q8_0 draft + ple/ CIRUPLE1 sidecar (mandatory).
MODEL_DIR=/home/dank/models/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4
MODEL_FILE=Qwen3.8-Flash-CIRU-STRIX-IU4.gguf
# Qwen-Sharp chat template (tracked in the repo, staged on the host). The
# Sharp template drives thinking on by default (medium effort); the server
@@ -52,24 +53,28 @@ ALIAS=frank-default-large
BIND_ADDR=0.0.0.0
LISTEN_PORT=7770
# Serving: f16 KV, context checkpoints, prompt cache. The model is 113.47
# GiB loaded via mmap into the Strix Halo unified memory pool (116 GiB
# SVM-backed). PLE table (50.66 GiB Q8_0) is streamed from page cache; never
# enters GPU VRAM. GPU resident: ~63-69 GiB. --fit off avoids the auto-fit
# segfault on this model's qwen4exp hyper-connection/indexer configuration.
CTX_SIZE=524288
PARALLEL=2
BATCH_SIZE=4096
UBATCH_SIZE=4096
NUM_THREADS=16
THREAD_BATCH=16
# Vendor production profile, verbatim: 262144-token context on ONE slot
# (parallel 1), batch 2048 / ubatch 512, 8+8 threads, f16 KV, 32 context
# checkpoints with min step 8192, 8 GiB prompt cache, 4 GiB PLE page cache.
# --fit off: auto-fit segfaults on this model's hyper-connection/indexer
# config; -ngl all puts every layer on the SVM-backed GPU pool.
CTX_SIZE=262144
PARALLEL=1
BATCH_SIZE=2048
UBATCH_SIZE=512
NUM_THREADS=8
THREAD_BATCH=8
CACHE_TYPE_K=f16
CACHE_TYPE_V=f16
CTX_CHECKPOINTS=16
CTX_CHECKPOINTS=32
CHECKPOINT_MIN_STEP=8192
CACHE_RAM=8192
PLE_CACHE_MIB=4096
SLOT_SAVE_PATH=/home/dank/serverAppConfigs/scripts/slot-state
SPLIT_MODE=none
FIT=off
# Sampling (Sharp default).
# Sampling (Sharp default; vendor API examples agree for non-thinking mode).
TEMPERATURE=0.7
TOP_K=20
TOP_P=0.8
@@ -78,7 +83,8 @@ PRESENCE_PENALTY=1.5
# Reasoning on (Sharp template drives it; preserve_thinking + preserve_reasoning
# keep the reasoning trail in the conversation). DeepSeek format projects the
# reasoning into the API's reasoning_content field instead of content tags.
# reasoning into the API's reasoning_content field instead of literal thinking
# tags.
REASONING=on
REASONING_FORMAT=deepseek
@@ -87,18 +93,26 @@ HSA_OVERRIDE_GFX_VERSION=11.5.1
VERBOSITY=4
# MTP draft head (speculative decoding) — BOTH attempted heads are
# INCOMPATIBLE with the STRIX_LEAN Uncensored model (missing tensor
# blk.0.hc_attn_norm.weight): the EasiiX Q8_0 and the agentionai
# ROCmFP4-FAST. Using ngram-mod only until a compatible MTP head
# is found. Set SPEC_TYPE=none to disable spec decoding entirely.
DRAFT_MODEL_DIR=/home/dank/models/mtp-Qwen3.8-Flash-Next-FAST
DRAFT_MODEL_FILE=Qwen3.8-Flash-Next-MTP-ROCmFP4-FAST.gguf
SPEC_TYPE=ngram-mod
# Speculative decoding: MTP draft head (Q8_0) at depth 3, p-split 0.10 —
# the vendor headline profile. ngram-mod stacking is a later experiment;
# SPEC_TYPE=none disables spec decoding entirely.
DRAFT_MODEL_DIR=/home/dank/models/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4/mtp
DRAFT_MODEL_FILE=Qwen3.8-Flash-CIRU-STRIX-IU4-MTP-Q8_0.gguf
SPEC_TYPE=draft-mtp
SPEC_DRAFT_N_MAX=3
SPEC_DRAFT_N_MIN=0
SPEC_DRAFT_P_MIN=0.75
SPEC_DRAFT_NGL=999
SPEC_DRAFT_P_MIN=0.0
SPEC_DRAFT_P_SPLIT=0.10
SPEC_DRAFT_NGL=all
SPEC_DRAFT_DEVICE=ROCm0
SPEC_DRAFT_TYPE_K=f16
SPEC_DRAFT_TYPE_V=f16
SPEC_DRAFT_TYPE_K=q8_0
SPEC_DRAFT_TYPE_V=q8_0
# Vendor runtime env knobs (read by the hipified mmq + PLE pager kernels).
# GGML_CUDA_Q41_MOE_FORCE_J forces the Q4_1 MoE WMMA tile width; the PLE
# pager knobs control the CIRUPLE1 page-in workers and skip re-hashing the
# 52 GB payload at every launch (checksums were verified once, at download).
GGML_CUDA_Q41_MOE_FORCE_J=32
GGML_QWEN4EXP_PLE_WORKERS=16
GGML_QWEN4EXP_PLE_STRICT_SHA=0
ROCBLAS_USE_HIPBLASLT=1
+72 -54
View File
@@ -1,35 +1,28 @@
#!/usr/bin/env bash
# Serve kingjones777/Qwen3.8-Flash-Next-ROCmFP4-STRIX as
# frank-default-large via the charlie12345/ROCmFPX llama.cpp fork with
# PR #27742 (qwen4exp architecture) merged, on Dankclaw (Strix Halo
# gfx1151, unified memory).
# Serve jcbtc/Qwen3.8-Flash-CIRU-STRIX-IU4 as frank-default-large via the
# ciru-ai/Qwen3.8-Flash-CIRU-STRIX-IU4 llama.cpp runtime (tag v1.1) on
# Dankclaw (Strix Halo gfx1151, unified memory).
#
# Runtime: ROCmFPX llama.cpp built at
# /home/dank/GitPackages/ROCmFPX/build-qwen38/bin/llama-server
# with -DGGML_HIP=ON -DGGML_HIP_ROCMI4_W4A4=ON
# -DCMAKE_HIP_ARCHITECTURES=gfx1151 -DLLAMA_BUILD_WEBUI=OFF.
# Runtime: ciru-ai Qwen3.8-Flash-CIRU-STRIX-IU4 llama.cpp built at
# /home/dank/GitPackages/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4/build-gfx1151
# with the vendor build-linux-amd.sh flag set (HIP on, HIP_NO_VMM on,
# HIP_GRAPHS on, HIP_MMQ_MFMA on, CUDA/VULKAN/SYCL off, gfx1151) PLUS
# -DGGML_CUDA_FA=ON -DGGML_CUDA_FA_ALL_QUANTS=ON. The Q4_1_MOE_FORCE_J and
# PLE env knobs below are read by the hipified mmq/pager kernels.
#
# Model: 177B params (56B MoE + 51.2B PLE n-gram table). 512 experts,
# 10 used, 48 layers (12 attention + 36 SSM/Mamba,
# full_attention_interval=4), 2 KV heads x 256 dim, QSA
# indexer (4 heads, top_k=2048), hyper-connections (count=4, low_rank=320),
# PLE (layer 1). Q4_0_ROCMFP4_STRIX quant, 113.47 GiB, single file.
# PLE table (50.66 GiB Q8_0) streamed from page cache; never in GPU VRAM.
# GPU resident: ~63-69 GiB. Context: up to 131072.
# Loaded with mmap (default) into the Strix Halo unified memory pool.
# --fit off is set because the auto-fit code segfaults on this model's
# hyper-connection/indexer configuration; -ngl 999 places all layers on
# the GPU (SVM-backed).
# Model: Qwen3.8-Flash-Next base (56B MoE, 512 experts / 10 used, 48 layers
# = 12 attention + 36 SSM, QSA indexer, hyper-connections, PLE at layer 1)
# in the CIRU quality-first mixed quant: 144 routed-expert tensors at Q4_1
# on the native IU4 WMMA path, protected tensors at Q5_K/Q5_1/Q8_0/BF16/F32.
# The exact-FP8 PLE table is a sidecar (ple/ dir) paged from disk through the
# CIRUPLE1 pager with a ple-cache-mib decoded-page cache; it never enters
# VRAM. The MTP draft head (Q8_0) drives speculative decoding at depth 3.
#
# MTP draft head: both attempted heads (EasiiX Q8_0 and agentionai
# ROCmFP4-FAST) are INCOMPATIBLE with the STRIX_LEAN model — the
# qwen4exp binary expects blk.0.hc_attn_norm.weight which neither
# draft GGUF carries. Using ngram-mod only. Set SPEC_TYPE=none in
# the env to disable spec decoding.
#
# The Qwen-Sharp chat template (scripts/chat-template.jinja) is applied at
# runtime so the model emits reasoning in DeepSeek format; the reasoning
# trail is preserved across turns via CHAT_TEMPLATE_KWARGS.
# Vendor production profile is applied verbatim on the first deployment:
# -ngl all, -sm none, --fit off, ctx 262144 x 1 slot, b 2048 / ub 512,
# t 8 / tb 8, f16 KV, fa on, cont-batching, prompt cache + 8 GiB cache-ram
# + idle-slot cache, 32 ctx checkpoints with min step 8192, MTP depth 3
# with p-split 0.10. Deviations from the vendor launcher are marked below.
set -euo pipefail
SCRIPT_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")" && pwd)"
@@ -42,24 +35,28 @@ if [[ -f "$ENV_FILE" ]]; then
fi
# --- defaults (used when the env file does not set them) -------------------
: "${LLAMA_BIN:=/home/dank/GitPackages/ROCmFPX/build-qwen38/bin/llama-server}"
: "${MODEL_DIR:=/home/dank/models/kingjones-Qwen3.8-Flash-Next-ROCmFP4-STRIX}"
: "${MODEL_FILE:=Qwen3.8-Flash-Next-Q4_0-ROCmFP4-STRIX.gguf}"
: "${LLAMA_BIN:=/home/dank/GitPackages/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4/build-gfx1151/bin/llama-server}"
: "${MODEL_DIR:=/home/dank/models/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4}"
: "${MODEL_FILE:=Qwen3.8-Flash-CIRU-STRIX-IU4.gguf}"
: "${CHAT_TEMPLATE_FILE:=$SCRIPT_DIR/chat-template.jinja}"
: "${CHAT_TEMPLATE_KWARGS:={}}"
: "${ALIAS:=frank-default-large}"
: "${BIND_ADDR:=0.0.0.0}"
: "${LISTEN_PORT:=7770}"
: "${CTX_SIZE:=524288}"
: "${PARALLEL:=2}"
: "${BATCH_SIZE:=4096}"
: "${UBATCH_SIZE:=4096}"
: "${NUM_THREADS:=16}"
: "${THREAD_BATCH:=16}"
: "${CTX_SIZE:=262144}"
: "${PARALLEL:=1}"
: "${BATCH_SIZE:=2048}"
: "${UBATCH_SIZE:=512}"
: "${NUM_THREADS:=8}"
: "${THREAD_BATCH:=8}"
: "${CACHE_TYPE_K:=f16}"
: "${CACHE_TYPE_V:=f16}"
: "${CTX_CHECKPOINTS:=16}"
: "${CTX_CHECKPOINTS:=32}"
: "${CHECKPOINT_MIN_STEP:=8192}"
: "${CACHE_RAM:=8192}"
: "${PLE_CACHE_MIB:=4096}"
: "${SLOT_SAVE_PATH:=$SCRIPT_DIR/slot-state}"
: "${SPLIT_MODE:=none}"
: "${FIT:=off}"
: "${TEMPERATURE:=0.7}"
: "${TOP_K:=20}"
@@ -69,19 +66,20 @@ fi
: "${REASONING:=on}"
: "${REASONING_FORMAT:=deepseek}"
: "${HSA_OVERRIDE_GFX_VERSION:=11.5.1}"
: "${SPEC_TYPE:=ngram-mod}"
: "${DRAFT_MODEL_DIR:=$MODEL_DIR}"
: "${DRAFT_MODEL_FILE:=Qwen3.8-Flash-Next-MTP-ROCmFP4-FAST.gguf}"
: "${SPEC_TYPE:=draft-mtp}"
: "${DRAFT_MODEL_DIR:=$MODEL_DIR/mtp}"
: "${DRAFT_MODEL_FILE:=Qwen3.8-Flash-CIRU-STRIX-IU4-MTP-Q8_0.gguf}"
: "${SPEC_DRAFT_N_MAX:=3}"
: "${SPEC_DRAFT_N_MIN:=0}"
: "${SPEC_DRAFT_P_MIN:=0.75}"
: "${SPEC_DRAFT_NGL:=999}"
: "${SPEC_DRAFT_P_MIN:=0.0}"
: "${SPEC_DRAFT_P_SPLIT:=0.10}"
: "${SPEC_DRAFT_NGL:=all}"
: "${SPEC_DRAFT_DEVICE:=ROCm0}"
: "${SPEC_DRAFT_TYPE_K:=f16}"
: "${SPEC_DRAFT_TYPE_V:=f16}"
: "${SPEC_DRAFT_TYPE_K:=q8_0}"
: "${SPEC_DRAFT_TYPE_V:=q8_0}"
MODEL="$MODEL_DIR/$MODEL_FILE"
for f in "$LLAMA_BIN" "$MODEL" "$CHAT_TEMPLATE_FILE"; do
for f in "$LLAMA_BIN" "$MODEL"; do
if [[ ! -r "$f" ]]; then
echo "missing or unreadable required artifact: $f" >&2
exit 1
@@ -92,9 +90,9 @@ if [[ ! -x "$LLAMA_BIN" ]]; then
exit 1
fi
# --- speculative decoding (MTP draft head) --------------------------------
# The MTP draft head is loaded as a separate GGUF sidecar via --model-draft.
# ngram-only specs (ngram-mod, etc.) do NOT need a draft model file.
# --- speculative decoding (MTP draft head) ---------------------------------
# The MTP draft head is a separate GGUF sidecar loaded via --spec-draft-model
# (alias --model-draft). ngram-only specs do not need a draft file.
# Set SPEC_TYPE=none in the env to disable speculative decoding entirely.
SPEC_ARGS=()
if [[ -n "$SPEC_TYPE" && "$SPEC_TYPE" != "none" ]]; then
@@ -111,16 +109,27 @@ if [[ -n "$SPEC_TYPE" && "$SPEC_TYPE" != "none" ]]; then
exit 1
fi
SPEC_ARGS+=(
--model-draft "$DRAFT_MODEL"
--spec-draft-model "$DRAFT_MODEL"
--spec-draft-ngl "$SPEC_DRAFT_NGL"
--spec-draft-device "$SPEC_DRAFT_DEVICE"
--spec-draft-type-k "$SPEC_DRAFT_TYPE_K"
--spec-draft-type-v "$SPEC_DRAFT_TYPE_V"
)
fi
if [[ -n "${SPEC_DRAFT_P_SPLIT:-}" ]]; then
SPEC_ARGS+=(--spec-draft-p-split "$SPEC_DRAFT_P_SPLIT")
fi
fi
SERVER_DIR="$(cd -- "$(dirname -- "$LLAMA_BIN")" && pwd)"
# The CIRU package is text-only: no mmproj sidecar. Pass --mmproj only when
# MMPROJ_PATH points at a readable file (kept for future multimodal packs).
MMPROJ_ARGS=()
if [[ -n "${MMPROJ_PATH:-}" && -r "${MMPROJ_PATH:-}" ]]; then
MMPROJ_ARGS=(--mmproj "$MMPROJ_PATH")
fi
SERVER_DIR="$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")" && pwd)"
mkdir -p "$SLOT_SAVE_PATH"
ROCM_PATH="${ROCM_PATH:-/opt/rocm}"
LIBRARY_PATH="$SERVER_DIR:$ROCM_PATH/lib:$ROCM_PATH/lib/rocm_sysdeps/lib:$ROCM_PATH/lib/llvm/lib${LD_LIBRARY_PATH:+:$LD_LIBRARY_PATH}"
@@ -129,6 +138,10 @@ exec /usr/bin/env \
HIP_VISIBLE_DEVICES=0 \
LD_LIBRARY_PATH="$LIBRARY_PATH" \
HSA_OVERRIDE_GFX_VERSION="$HSA_OVERRIDE_GFX_VERSION" \
GGML_CUDA_Q41_MOE_FORCE_J="${GGML_CUDA_Q41_MOE_FORCE_J:-32}" \
GGML_QWEN4EXP_PLE_WORKERS="${GGML_QWEN4EXP_PLE_WORKERS:-16}" \
GGML_QWEN4EXP_PLE_STRICT_SHA="${GGML_QWEN4EXP_PLE_STRICT_SHA:-0}" \
ROCBLAS_USE_HIPBLASLT="${ROCBLAS_USE_HIPBLASLT:-1}" \
"$LLAMA_BIN" \
--model "$MODEL" \
--alias "$ALIAS" \
@@ -138,7 +151,8 @@ exec /usr/bin/env \
--port "$LISTEN_PORT" \
--jinja \
--device ROCm0 \
--gpu-layers 999 \
--gpu-layers "${NGL:-all}" \
--split-mode "$SPLIT_MODE" \
--parallel "$PARALLEL" \
--ctx-size "$CTX_SIZE" \
--batch-size "$BATCH_SIZE" \
@@ -150,7 +164,11 @@ exec /usr/bin/env \
--threads "$NUM_THREADS" \
--threads-batch "$THREAD_BATCH" \
--ctx-checkpoints "$CTX_CHECKPOINTS" \
--checkpoint-min-step "$CHECKPOINT_MIN_STEP" \
--cache-ram "$CACHE_RAM" \
--ple-sidecar "$MODEL_DIR/ple" \
--ple-cache-mib "$PLE_CACHE_MIB" \
--slot-save-path "$SLOT_SAVE_PATH" \
--cache-prompt \
--cache-idle-slots \
--metrics \
@@ -162,5 +180,5 @@ exec /usr/bin/env \
--reasoning "$REASONING" \
--reasoning-format "$REASONING_FORMAT" \
--reasoning-budget -1 \
--mmproj "$MMPROJ_PATH" \
"${SPEC_ARGS[@]}"
"${MMPROJ_ARGS[@]}" \
"${SPEC_ARGS[@]}"