docs: dankserver board swap clears the PCIe-atomics wall

Reanalysis after the 2026-09-20 swap to an ASUS ProArt B850-Creator WiFi
NEO: both R9700s now sit on CPU GPP root ports (x8/x8 Gen5 bifurcation),
every bridge reads AtomicOpsCap Routing+, and both endpoints read
AtomicOpsCtl ReqEn+ (CAP_EXP+28.w = 0x1440) — the exact precondition
Dual-R9700-Cooperation's test plan named. TP=2 is therefore unblocked,
not proven: no collective has been dispatched since the swap,
GGML_HIP_RCCL is still OFF, and the 272 t/s "tensor" number on record
measured a butterfly fallback.

- Dual-R9700-Cooperation: short answer rewritten, re-measured 2026-09-20
  topology table, rebuild-hypothesis door marked moot, probe plan is now
  standing work.
- Dankserver System Specs: Motherboard section; GPU BDFs 0b:00.0 ->
  07:00.0, iGPU 10:00.0 -> 11:00.0, kernel 7.0.0-31, SMT on, and the new
  eno2 (192.168.0.247) second 5GbE port holding the low-metric default
  route while eno1 keeps the fleet's static .235.
- frank-medium-llamacpp-dflash2: rationale and hardware row split past
  from present; dated work-log sections stay as history.
- AGENTS.md + both indexes: no longer assert a wall that no longer exists.

Docs only; frank-medium stayed active and healthy throughout (verified
/health). ./tests/run.sh 331/331.

AGENTS.md

@@ -24,7 +24,7 @@ merge absorbed the former `vllmScripts` repo, history preserved).
 
 | Target | Service | Runtime | Model | Port |
 |--------|---------|---------|-------|------|
-|Dankserver|`frank-medium`|mainline llama.cpp master fb27a525 (root systemd unit, gfx1201 HIP build)|orcarouter Qwen3.8-27B-Uncensored Q8_0 with the z-lab DFlash2 Q4_K_M drafter (the model's own MTP head stays in the file, one SPEC_TYPE change away), 2x Radeon AI PRO R9700 in ONE layer-split process (32:33 balanced; ROCm0 Gen4 x16, ROCm1 Gen4 x1 chipset path), 327680 ctx over 2 slots of 163840, batch 6144x512, f16 KV + 16 GiB host-RAM prompt cache, vision (BF16 mmproj)|7770|
+|Dankserver|`frank-medium`|mainline llama.cpp master fb27a525 (root systemd unit, gfx1201 HIP build)|orcarouter Qwen3.8-27B-Uncensored Q8_0 with the z-lab DFlash2 Q4_K_M drafter (the model's own MTP head stays in the file, one SPEC_TYPE change away), 2x Radeon AI PRO R9700 in ONE layer-split process (32:33 balanced; both cards on CPU root ports at Gen5 x8 since the 2026-09-20 ProArt B850-Creator swap — atomic routing verified on both chains), 327680 ctx over 2 slots of 163840, batch 6144x512, f16 KV + 16 GiB host-RAM prompt cache, vision (BF16 mmproj)|7770|
 | Dankclaw | `frank-large` | CIRU v4.4.1 llama.cpp (QSA window hotfix, root systemd unit, gfx1151 HIP build) | jcbtc Qwen3.8-Flash-CIRU-STRIX-Orca on the gfx1151 iGPU (Strix Halo LPDDR), 262144 ctx single stream (1 slot), MTP depth 4, PLE 4096 MiB, text only | 7770 |
 | Dankclaw | `frank-small` | mainline llama.cpp master 37b53fd (root systemd unit) | HauhauCS Gemma4-12B-QAT-Uncensored-Balanced Q4_K_M (BF16 mmproj + MTP assistant sidecar, `draft-mtp,ngram-mod`) on the RTX 3090, 1048576 pool / 4 slots of 262,144, q8_0 KV, the fleet's vision endpoint | 7771 |
 
@@ -337,10 +337,13 @@ model's own MTP head (`blk.<n>.nextn.*`, `nextn_predict_layers=1`), so
 **one process across both R9700s**, `--split-mode layer` at a **32:33 tensor
 split** — balanced (operator call 2026-09-19, the most even split 65 layers
 allow; ROCm1, the last-layers card that also carries the drafter and output
-layers, holds the extra one). The predecessor's 35:30 skew (2026-09-17) leaned
-work onto the x16 card because ROCm1 (0b:00.0) rides the B650 chipset at Gen4
-x1 (~1.97 GB/s) while ROCm0 (03:00.0) is CPU-root-port Gen4 x16 (~31.5 GB/s);
-the balanced point trades that lean for symmetry and was accepted. 327680 ctx
+layers, holds the extra one).
+The predecessor's 35:30 skew (2026-09-17) leaned work onto the wider card
+because ROCm1 (then `0b:00.0`) rode the B650 chipset at Gen4 x1 (~1.97 GB/s)
+against ROCm0's CPU-root-port Gen4 x16 (~31.5 GB/s); the balanced point traded
+that lean for symmetry and was accepted. The 2026-09-20 board swap (ASUS ProArt
+B850-Creator WiFi NEO) removed the other axis: both cards are now CPU-root-port
+Gen5 x8 (~31.5 GB/s each), at `03:00.0` and `07:00.0`. 327680 ctx
 over **2 slots** of 163840 — inside the checkpoint's trained 262144 window, so
 no rope extrapolation (unlike the predecessor's 393216) — batch 6144x512, f16
 KV, a 16384 MiB host-RAM prompt cache, vision via the BF16 mmproj. DSpark was
@@ -348,13 +351,18 @@ tried in the drafter's place on 2026-09-16 and reverted: it declares no sliding
 window, so its draft KV spanned the whole context (5.0 GiB) and cost ROCm1 four
 layers of the split.
 
-**Layer split is why both cards now serve ONE model.** Tensor parallelism is
-impossible (see the PCIe lesson below), and so is vLLM's pipeline parallelism —
-its stage handoff is an RCCL `send`/`recv` of the hidden state, the exact
-primitive that cannot be dispatched on card #2. llama.cpp's layer split needs
+**Layer split is why both cards serve ONE model today.** It was chosen because
+tensor parallelism was then impossible (see the PCIe lesson below) and so was
+vLLM's pipeline parallelism — its stage handoff is an RCCL `send`/`recv` of the
+hidden state, the exact primitive that could not be dispatched on the old
+board's card #2. llama.cpp's layer split needs
 no collective at all: layers are distributed in order and the boundary
 activation is a per-backend copy, once per forward pass. Measured on this host
-(the predecessor runtime): 1991 t/s prefill layer-split vs 272 tensor.
+(the predecessor runtime): 1991 t/s prefill layer-split vs 272 tensor — but that
+tensor number is the cost of a butterfly-fallback allreduce with `GGML_HIP_RCCL`
+OFF, not what an RCCL-backed tensor split would do. Since the 2026-09-20 board
+swap cleared the atomics gate, that comparison is stale and the probe is the
+open work; see [[Dual-R9700-Cooperation]].
 
 This is the box's **only** LLM runtime: the vllm-radiance replica pair and its
 routing proxy (`frank-medium-a/-b/-proxy`) were retired the same day they went
@@ -396,25 +404,27 @@ linked runbooks.
   and the rest behind the chipset (usually not) — that asymmetry is what
   blocked frank-medium's TP=2. A one-card collective proves nothing: NCCL
   short-circuits at `world_size=1`.
-- **The fix is physical — and cheap on this board.** Two paths put both cards
-  on CPU root ports, which restores the atomics routing and therefore TP=2: an
-  M.2→PCIe x4 riser into a *CPU-attached* M.2 slot (on dankserver's TUF
-  GAMING B650-E WIFI that is M.2_2, which is free — per ASUS's spec page;
-  `PCIEX16_2`, where card #2 sits today, is chipset and x1-mode), or a board
-  whose CPU x16 bifurcates to x8/x8. Bandwidth is not the constraint: a 27B
-  TP=2 allreduce at batch 4 is ≈10 MB per token-step, ≈1.4 ms at Gen4 x4.
-  RCCL's P2P `send`/`recv` fails on such a card too, so pipeline parallelism is
-  not an escape either. Full evidence matrix, the open rebuild hypothesis, and
-  the test plan: [[Dual-R9700-Cooperation]].
+- **That wall was physical, and it was fixed on 2026-09-20 by a board swap.**
+  Both paths that put two cards on CPU root ports were: an M.2→PCIe x4 riser
+  into a *CPU-attached* M.2 slot, or a board whose CPU lanes bifurcate to
+  x8/x8. dankserver took the second: **ASUS ProArt B850-Creator WiFi NEO**,
+  `PCIEX16_1` + `PCIEX16_2` at x8/x8 Gen5 on root ports `00:01.1` / `00:01.3`,
+  every bridge now `Routing+` and **both endpoints `ReqEn+`** — the exact
+  precondition the old test plan named. Bandwidth was never the constraint (a
+  27B TP=2 allreduce at batch 4 is ≈10 MB per token-step, ≈1.4 ms at Gen4 x4
+  and under 0.4 ms at Gen5 x8). **What is NOT yet re-measured:** no collective
+  has been dispatched since the swap, so TP=2 is unblocked, not proven. Full
+  evidence matrix and the standing probe plan: [[Dual-R9700-Cooperation]].
 - **When a GPU collective dies, read the runtime, not the framework.** The
   message that identified the cause came from `AMD_LOG_LEVEL=3`
   (`Pcie atomics not enabled, hostcall not supported` → `AQL dispatch
   failed!`), not from vLLM or RCCL. `AMD_LOG_LEVEL` costs one env var and
   prints the failing HIP call with its return code.
-- **The one software path that lets both cards serve ONE model: llama.cpp's
-  layer split.** vLLM cannot do it here in any of its parallelisms — TP needs
-  an allreduce, PP needs the same p2p primitive, and both die on the card that
-  cannot dispatch an RCCL kernel. `--split-mode layer` in llama.cpp needs no
+- **The software path that puts both cards on ONE model without a collective:
+  llama.cpp's layer split.** On the old board vLLM could not do it in any of its
+  parallelisms — TP needs an allreduce, PP needs the same p2p primitive, and both
+  died on the card that could not dispatch an RCCL kernel. `--split-mode
+  layer` in llama.cpp needs no
   collective: layers are distributed in order and only the boundary activation
   crosses PCIe, once per forward pass. Measured here: 1991 t/s prefill /
   18.8 tok/s decode layer-split, against 272 / 26.3 tensor (butterfly