# Tunables for frank-default-large (jcbtc/Qwen3.8-Flash-CIRU-STRIX-IU4 on
# the ciru-ai Qwen3.8-Flash-CIRU-STRIX-IU4 llama.cpp runtime, tag v1.1,
# Dankclaw, Strix Halo gfx1151 unified memory).
#
# Runtime: full llama.cpp fork at
# /home/dank/GitPackages/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4/build-gfx1151,
# built with the vendor build-linux-amd.sh flag set (HIP on, HIP_NO_VMM on,
# HIP_GRAPHS on, HIP_MMQ_MFMA on, CUDA/VULKAN/SYCL off, gfx1151) plus
# GGML_CUDA_FA + GGML_CUDA_FA_ALL_QUANTS. The IU4 WMMA expert path and the
# CIRUPLE1 PLE pager read the GGML_* env knobs exported by the serve script.
# Replaced the kingjones STRIX_LEAN (ROCmFPX build-qwen38) deployment.
#
# Model: Qwen3.8-Flash-Next base (56B MoE, 512 experts / 10 used, 48 layers
# = 12 attention + 36 SSM, QSA indexer, hyper-connections, PLE at layer 1)
# in the CIRU quality-first mixed quant: 144 routed-expert tensors at Q4_1
# on the native IU4 WMMA path, protected tensors at Q5_K/Q5_1/Q8_0/BF16/F32.
# Main GGUF ~79 GB + MTP Q8_0 draft ~4 GB + exact-FP8 PLE sidecar ~52 GB
# paged from disk (never in VRAM; 4 GiB decoded-page cache via
# --ple-cache-mib). Vendor-validated on the same silicon (gfx1151).
#
# The vendor production profile is applied verbatim on this first deployment:
# -ngl all, -sm none, --fit off, ctx 262144 x 1 slot, b 2048 / ub 512,
# t 8 / tb 8, f16 KV, fa on, cont-batching, prompt cache + 8 GiB cache-ram
# + idle-slot cache, 32 ctx checkpoints with min step 8192, MTP depth 3
# with p-split 0.10, GGML_CUDA_Q41_MOE_FORCE_J=32,
# GGML_QWEN4EXP_PLE_WORKERS=16, GGML_QWEN4EXP_PLE_STRICT_SHA=0 (checksums
# were verified with sha256sum -c at download time), ROCBLAS_USE_HIPBLASLT=1.
# The Qwen-Sharp chat template is kept on purpose (chat-template.jinja): the
# service keeps emitting reasoning in DeepSeek format for its clients.
#
# WARNING: do not name any variable TEMP, HOST, or GPU_MAX_HEAP_SIZE. The
# ROCm HIP runtime reads those bare env vars (see the 2026-08-13 TEMP
# incident). llama.cpp reads --host/--port/--temp as CLI flags, never as
# env vars.

# CIRU v1.1 runtime binary (vendor build script, plus FA_ALL_QUANTS).
LLAMA_BIN=/home/dank/GitPackages/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4/build-gfx1151/bin/llama-server

# Model package from https://huggingface.co/jcbtc/Qwen3.8-Flash-CIRU-STRIX-IU4
# Layout: main GGUF + mtp/ Q8_0 draft + ple/ CIRUPLE1 sidecar (mandatory).
MODEL_DIR=/home/dank/models/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4
MODEL_FILE=Qwen3.8-Flash-CIRU-STRIX-IU4.gguf

# Qwen-Sharp chat template (tracked in the repo, staged on the host). The
# Sharp template drives thinking on by default (medium effort); the server
# emits reasoning in DeepSeek format so clients receive reasoning_content
# separately instead of literal thinking tags in content.
CHAT_TEMPLATE_FILE=/home/dank/serverAppConfigs/scripts/chat-template.jinja
CHAT_TEMPLATE_KWARGS='{"enable_thinking":true,"preserve_thinking":true,"preserve_reasoning":true}'

# Alias + network.
ALIAS=frank-default-large
BIND_ADDR=0.0.0.0
LISTEN_PORT=7770

# Vendor production profile, verbatim: 262144-token context on ONE slot
# (parallel 1), batch 2048 / ubatch 512, 8+8 threads, f16 KV, 32 context
# checkpoints with min step 8192, 8 GiB prompt cache, 4 GiB PLE page cache.
# --fit off: auto-fit segfaults on this model's hyper-connection/indexer
# config; -ngl all puts every layer on the SVM-backed GPU pool.
CTX_SIZE=262144
PARALLEL=1
BATCH_SIZE=2048
UBATCH_SIZE=512
NUM_THREADS=8
THREAD_BATCH=8
CACHE_TYPE_K=f16
CACHE_TYPE_V=f16
CTX_CHECKPOINTS=32
CHECKPOINT_MIN_STEP=8192
CACHE_RAM=8192
PLE_CACHE_MIB=4096
SLOT_SAVE_PATH=/home/dank/serverAppConfigs/scripts/slot-state
SPLIT_MODE=none
FIT=off

# Sampling (Sharp default; vendor API examples agree for non-thinking mode).
TEMPERATURE=0.7
TOP_K=20
TOP_P=0.8
MIN_P=0.0
PRESENCE_PENALTY=1.5

# Reasoning on (Sharp template drives it; preserve_thinking + preserve_reasoning
# keep the reasoning trail in the conversation). DeepSeek format projects the
# reasoning into the API's reasoning_content field instead of literal thinking
# tags.
REASONING=on
REASONING_FORMAT=deepseek

# Strix Halo unified memory + native gfx1151.
HSA_OVERRIDE_GFX_VERSION=11.5.1

VERBOSITY=4

# Speculative decoding: MTP draft head (Q8_0) at depth 3, p-split 0.10 —
# the vendor headline profile. ngram-mod stacking is a later experiment;
# SPEC_TYPE=none disables spec decoding entirely.
DRAFT_MODEL_DIR=/home/dank/models/ciru-Qwen3.8-Flash-CIRU-STRIX-IU4/mtp
DRAFT_MODEL_FILE=Qwen3.8-Flash-CIRU-STRIX-IU4-MTP-Q8_0.gguf
SPEC_TYPE=draft-mtp
SPEC_DRAFT_N_MAX=3
SPEC_DRAFT_N_MIN=0
SPEC_DRAFT_P_MIN=0.0
SPEC_DRAFT_P_SPLIT=0.10
SPEC_DRAFT_NGL=all
SPEC_DRAFT_DEVICE=ROCm0
SPEC_DRAFT_TYPE_K=q8_0
SPEC_DRAFT_TYPE_V=q8_0

# Vendor runtime env knobs (read by the hipified mmq + PLE pager kernels).
# GGML_CUDA_Q41_MOE_FORCE_J forces the Q4_1 MoE WMMA tile width; the PLE
# pager knobs control the CIRUPLE1 page-in workers and skip re-hashing the
# 52 GB payload at every launch (checksums were verified once, at download).
GGML_CUDA_Q41_MOE_FORCE_J=32
GGML_QWEN4EXP_PLE_WORKERS=16
GGML_QWEN4EXP_PLE_STRICT_SHA=0
ROCBLAS_USE_HIPBLASLT=1