docs(iommu): correct the identity-mode cost claim; pt is most of the fix, PerfOpt the last part

Reading patch v2 1/2 verbatim: amd_iommu_enable_perfopt() rehoming needs the
device ALREADY on the identity domain and switches ATS/PRI/PASID/GCR3 off via
the skip_caps path. So an iGPU in identity mode still pays a 1:1 page walk plus
those four capabilities until PerfOpt exists -- iommu=pt recovers most of the
gap, PerfOpt the last part. The first pass claimed pt alone already avoids the
cost; that was wrong and is retracted here and in the posted issue comment
(edit 23).

Also re-keys frank-npu.md, which carried the dead law 'iommu=pt is not a middle
ground' as its retirement rationale: identity mode + SVA is exactly the revival
path (amdxdna binds its own IOPT_TYPE_SVA domain), and the cost is single-digit
percent on this silicon class. Procedure step 2 now demands a local off-vs-pt
measurement instead of inheriting the vendor's 13-16%, whose slow-arm boot line
our record never identified.

serverAppConfigs-docs/LLM/frank-npu.md

@@ -42,9 +42,21 @@ upstream project on this exact silicon. That single flag is the whole decision:
   out `/dev/accel/accel0` — every open fails with `err=-19` ("No such device").
   That is precisely the failure the endpoint was rescued from on 2026-08-30,
   recorded in the next section.
-- `iommu=pt` is not a middle ground for the NPU *and* the prefill number: the
-  passthrough domain still costs the prefill throughput the vendor measured.
-- The operator chose prefill, so the NPU endpoint goes.
+- `iommu=pt` was recorded here as "not a middle ground", on the theory that the
+  passthrough domain still costs the vendor's prefill number. **That claim did
+  not survive the 2026-10-18 research.** Identity mode is not free for the iGPU
+  — its DMA still walks 1:1 page tables and the AMD attach path enables
+  ATS/PRI/PASID/GCR3 for the device — but on this silicon class the cost is
+  single-digit percent, and **AMD PerfOpt** (Linux 7.4, merged 2026-09-24)
+  removes it: the IOMMU then enforces only the IR/IW permission bits for the
+  privileged iGPU and stays fully armed for every other device, the NPU
+  included. So `pt` IS the revival path for this endpoint. See
+  [[dankclaw-iommu-translation-off]] § *2026-10-18 research* for the kernel
+  census, the versions to avoid (6.18–6.18.7 disable SVA), the device-access
+  quadlet law (`AddDevice=/dev/accel/accel0` + `GroupAdd=keep-groups`), and the
+  measurement step that must precede any decision.
+- The operator took the vendor's prefill figure on the September evidence, so the
+  NPU endpoint went.
 
 Consequences accepted at retirement: **audio input left the fleet with no
 replacement** (halogen reads images only, no audio or video), and the surviving