frank-medium: shift the layer split to 35:30, leaning work onto the x16 card

The two R9700s sit on unequal PCIe paths: ROCm0 (03:00.0) is CPU-root-port
Gen4 x16 (~31.5 GB/s); ROCm1 (0b:00.0) rides the B650 chipset through
bridges negotiating Gen4 x1 (~1.97 GB/s).  With the MTP drafter, output
layers and heavier compute buffers pinned to the last-layers card, live
rocm-smi read 98% busy on the x1 card vs 40% on the x16 card.  Moving one
DeltaNet layer (34) to ROCm0 shifts ~0.43 GiB off the bottlenecked card;
the seam fit lands 30.59/30.01 with gap 0.58 GiB, inside floor and slack.
36:29 fails both gates, so this lever is spent.

serverAppConfigs-docs/LLM/frank-medium-llamacpp-dflash2.md

@@ -1,7 +1,7 @@
 ---
 type: configuration
 title: frank-medium llama.cpp Runbook (MTP drafter)
-description: The ACTIVE frank-medium deployment since 2026-09-16 — mainline llama.cpp on Dankserver serving ajgazin/Swift-Qwen3.8-27B-Uncensored-Dynamic-MTP at UD-Q8_K_XL with the model's own MTP head (the z-lab DFlash2 sidecar kept on disk, one env change away), as ONE layer-split process across both Radeon AI PRO R9700 cards at a 34:31 split, a 393216-position KV pool (196608 per conversation over two slots), vision via the BF16 mmproj.
+description: The ACTIVE frank-medium deployment since 2026-09-16 — mainline llama.cpp on Dankserver serving ajgazin/Swift-Qwen3.8-27B-Uncensored-Dynamic-MTP at UD-Q8_K_XL with the model's own MTP head (the z-lab DFlash2 sidecar kept on disk, one env change away), as ONE layer-split process across both Radeon AI PRO R9700 cards at a 35:30 split (skewed toward the x16-slot card; see the 2026-09-17 part 3 section), a 393216-position KV pool (196608 per conversation over two slots), vision via the BF16 mmproj.
 tags:
   - frank-medium
   - dankserver
@@ -145,7 +145,7 @@ Deployed flags:
 
 | Flag | Value | Why |
 |---|---|---|
-| `--split-mode` / `--device` / `--tensor-split` | `layer` / `ROCm0,ROCm1` / `34,31` | both cards, one model, no collective; the split is skewed because ROCm1 carries the drafter, and it is one LAYER of granularity — 0.43 GiB on a DeltaNet boundary, 1.43 GiB on an attention one. 34:31 is the balance point at the 393216 pool (gap 1.44 GiB in the fit); 35:30 and 36:29 fail the 1 GiB floor on card 0 at this pool |
+| `--split-mode` / `--device` / `--tensor-split` | `layer` / `ROCm0,ROCm1` / `35,30` | both cards, one model, no collective; the split is skewed because ROCm1 carries the drafter, and it is one LAYER of granularity — 0.43 GiB on a DeltaNet boundary, 1.43 GiB on an attention one. 35:30 since 2026-09-17 (part 3): ROCm0 is CPU-root-port Gen4 x16, ROCm1 rides the chipset at Gen4 x1, and the drafter-bound card on the x1 path ran 98% against the x16 card's 40%. 36:29 fails both the 1 GiB floor (card 0 free 0.45) and the fit slack (gap 2.22) — this is the farthest safe shift |
 | `--gpu-layers` / `--fit` | `999` / `off` | everything on the cards; auto-fit must not resize a context we set |
 | `--ctx-size` / `--parallel` | `393216` / `2` | the pool over two slots of 196608; `--parallel` **divides** the context. 1.5x the trained 262144 window, and the GGUF has no rope scaling — see the 2026-09-17 section |
 | `--batch-size` / `--ubatch-size` | `6144` / `512` | measured: ubatch 512 is the prefill optimum *and* the cheapest point on the curve; the logical batch is throughput- and VRAM-neutral. See [[frank-medium-batch-ubatch]] |
@@ -326,8 +326,10 @@ draft context is sized from the target, same law as the DFlash2 one) plus
 draft buffers the fit only estimated. The seam was recalibrated to the
 measured value: the MTP buffer constant is now 2,901,231,913 B (the 4.20 GiB
 total MTP charge on card 1), and the floor dropped 1.5 → **1.0 GiB** for this
-shape — ROCm1's 1.08 GiB of headroom is real, and 35:30/36:29 fail card 0's
-floor at this pool, so 34:31 is the only split that fits 2x196k.
+shape — ROCm1's 1.08 GiB of headroom is real. 35:30 failed card 0's floor
+only at the OLD 1.5 GiB bar (it clears 1.0 with 1.27 GiB to spare); 36:29
+fails both gates. Under the recalibrated 1.0 GiB floor 35:30 became
+reachable — and the split went there the same day (part 3).
 
 The rope caveat deepens: the top 131k of a conversation (196608 vs the
 trained 262144… i.e. 393216/2 = 196608 per slot, so the top 131,072 positions
@@ -339,6 +341,34 @@ Verified after deploy: `adding speculative implementation 'draft-mtp'` with
 present; 207 drafts / 108 accepted in a text run (52 % acceptance, mean len
 ~1.7); vision, tools and `reasoning_effort` all pass; e2e 32/32; `NRestarts=0`.
 
+## 2026-09-17 (part 3): the PCIe topology, and the split leans to 35:30
+
+`lspci -vv` on dankserver answers why the split now leans toward ROCm0:
+the two cards do not sit on equal roads.
+
+| Card | Path | Bottleneck link |
+|---|---|---|
+| ROCm0 `03:00.0` | CPU root port `00:01.1` (Gen4 x16) -> switch -> card | Gen4 **x16** (~31.5 GB/s) |
+| ROCm1 `0b:00.0` | CPU root port `00:02.1` (Gen4 x4) -> chipset -> `06:09.0` -> `09:00.0` -> card | Gen4 **x1** (~1.97 GB/s) |
+
+With the MTP drafter, the output layers and the heavier compute buffers
+all pinned to the last-layers card, live `rocm-smi` under traffic read
+**98% busy on the x1 card vs 40% on the x16 card**. The boundary crossing
+itself is cheap (~5.2 MB of activation per 512-token ubatch rides the
+wire — a few ms at 1.97 GB/s against a ~430 ms ubatch), but the
+saturated card should not be the one behind the narrowest link. The
+operator moved one layer to ROCm0: **34:31 -> 35:30**. The moved layer
+is 34 — the 4k+2 position of block 8, a DeltaNet — which is what keeps
+the shift cheap (~0.43 GiB).
+
+Fit at the new shape: card 0 30.59 GiB (free 1.27), card 1 30.01 GiB
+(free 1.85), gap 0.58 — inside the 1.0 GiB floor and the 1.483 GiB
+slack. The next step, 36:29, crosses the full-attention layer at 35 and
+fails BOTH gates (card 0 free 0.45 GiB, gap 2.22 GiB), so the
+layer-toward-ROCm0 lever is spent: further rebalancing means a ctx cut,
+not a layer. The seam's balance test re-derives all of this from the env
+file on every run.
+
 
 ## Verified serving behaviour (2026-09-16)